1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a line-on-glass liquid crystal display apparatus and driving method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for stably supplying a gate low voltage signal.
2. Description of the Related Art
In general, liquid crystal display (LCD) devices are non-emissive display devices and are commonly used in notebook and desktop computers because of their high resolution, color rendering capability, and high quality image display. A liquid crystal display device controls the light transmittance of liquid crystal using an electric field, thereby displaying a picture. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix shape and a drive circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged to cross each other, and sub-pixel units are located in areas defined by the crossing of the gate lines and the data lines. A common electrode is provided for all of the sub-pixel units. A pixel electrode is provided in each of the sub-pixel units. Each of the pixel electrodes is connected to one of the data lines through source and drain electrodes of a thin film transistor, which is a switching device within the sub-pixel unit corresponding to the pixel electrode. A gate electrode of the thin film transistor is connected to one of the gate lines.
The drive circuit includes a gate driver for driving the gate lines; a data driver for driving the data lines; a timing controller for controlling the gate driver and the data driver; and a power supply for supplying various drive voltages, which are used in the liquid crystal display (LCD) device. The timing controller controls drive timing of the gate driver and the data driver, and supplies a pixel data signal to the data driver. The power supply generates drive voltages, such as common voltage VCOM, gate high voltage VGH, and gate low voltage VGL, which are required to operate the liquid crystal display device.
The gate driver sequentially supplies a scan signal to the gate lines to sequentially drive the liquid crystal cells of the liquid crystal display panel, line by line. The data driver supplies a pixel voltage signal to each of the data lines while the scan signal is supplied to one of the gate lines. Accordingly, the liquid crystal display device controls the light transmittance by using electric fields applied between the pixel electrodes and the common electrode in accordance with the pixel voltage signals to each of the sub-pixel units, thereby displaying a picture.
The data driver and the gate driver are connected to the liquid crystal display panel. The data driver and the gate driver can be implemented as a plurality of integrated circuits (ICs). Both the data drive IC and the gate drive IC are mounted on a tape carrier package (TCP) connected to the liquid crystal display panel by a tape automated bonding (TAB) method or are mounted on the liquid crystal display panel by a chip on glass (COG) method.
The drive IC's connected to the liquid crystal display panel by the TAB method through the TCP are connected to each other and receive control signals and DC voltages input from the outside through the signal lines mounted on a printed circuit board (PCB), which is connected to the TCP. The data drive IC's are connected in series through signal lines on a data PCB and commonly receive a pixel data signal and control signals from the timing controller as well as drive voltages from the power supply. The gate drive IC's are connected in series through signal lines on a gate PCB and commonly receive the control signals from the timing controller and the drive voltages from the power supply. The drive IC's mounted on the liquid crystal display panel by the COG method are connected to each other by a line-on-glass (hereinafter, referred to as ‘LOG’) method where the signal lines are mounted directly on the liquid crystal display panel, such as a lower glass substrate of the LCD device, and receive the control signals and the drive voltages from the timing controller and the power supply.
Recently, even when drive IC's are being connected to the liquid crystal display panel by the TAB method, the PCB is removed by adopting the LOG method such that the LCD device can be made thinner. The signal lines connected to the gate drive IC's, which require relatively few signal lines, are formed on the liquid crystal display panel by the LOG method, thereby eliminating the need for the gate PCB. In other words, the gate drive IC's connected to the liquid crystal display panel by the TAB method are interconnected through signal lines mounted on the lower glass of the liquid crystal display panel, and commonly receive the control signals and the drive voltage signals (hereinafter, referred to as ‘gate drive signals’).
FIG. 1 is a plan view of a line-on-glass liquid crystal display device of the related art. A liquid crystal display device where LOG signal lines are used instead of the gate PCB, as shown in FIG. 1, includes: a liquid crystal display panel 1; a plurality of data TCP's 8 connected between the liquid crystal display panel 1 and a data PCB 12; a plurality of gate TCP's 14 connected to another side of the liquid crystal display panel 1; data drive IC's 10 mounted on the data TCP's 8 respectively; and gate drive IC's 16 mounted on the gate TCP's 14, respectively.
The liquid crystal display panel 1 includes a lower substrate 2 on which a thin film transistor array is formed together with various signal lines; an upper substrate 4 on which a color filter array is formed; and liquid crystal injected between the lower substrate 2 and the upper substrate 4. In such a liquid crystal display panel 1, there is provided a picture display area 21 having sub-pixel units provided in areas between the crossing gate lines 20 and data lines 18. In an outer area of the lower substrate 2, which is located outside of the picture display area 21, data pads connected to the data lines 18 and gate pads connected to the gate lines 20 are provided. Further, a LOG signal line group 26 for transmitting the gate drive signals, which are supplied to the gate drive IC 16, is provided in the outer area of the lower substrate 2.
The data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data drive IC 10 are provided on the data TCP 8. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 through an anisotropic conductive film (hereinafter, referred to as ‘ACF’), and the output pads 25 of the data TCP 8 are electrically connected to the data pads on the lower substrate 2 through the ACF. A gate drive signal transmission group 22 is electrically connected to the LOG signal line group 26 on the lower substrate 2 is also provided on a first data TCP 8. The gate drive signal transmission group 22 supplies the gate drive signals of the timing controller and the power supply to the LOG signal line group 26 from the data PCB 12. The data drive IC's 10 convert the pixel data signal from a digital signal into a pixel voltage signal, which is an analog signal, and then supplies the pixel voltage signal to the data lines 18 of the liquid crystal display panel.
The gate drive IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 are electrically connected to the gate drive IC 16 provided on the gate TCP 14. The gate drive signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2 through the ACF, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2 through the ACF. The gate drive IC's 16 sequentially supply a scan signal, such as a gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. Further the gate drive IC's 16 supply a gate low voltage signal VGL to the gate lines, except for the period when the gate high voltage signal VGH is supplied.
The LOG signal line group 26 includes signal lines that supply DC voltage signals from the power supply, such as the gate high voltage signal VGH, the gate low voltage signal VGL, a common voltage signal VCOM, a ground voltage signal GND and a power voltage signal VCC. Further, the LOG signal line group 26 also includes signal lines that supply and gate control signals from the timing controller, such as a gate start pulse GSC, a gate shift clock signal GSC and a gate enable signal GOE.
FIG. 2 is an equivalent circuit of a vertically adjacent gate line and a data line of a sub-pixel region in a related art liquid crystal display device. As shown in FIG. 2, in the case of a specific signal applied to the data line (data), there can be a high voltage difference between the data line (data) and the gate line. In the case of data having a high brightness difference between adjacent pixels in a vertical direction, a return current is generated in the gate line due to the coupling between the data line and the gate line by a parasitic capacitance. Such a return current may slightly turn on the vertically adjacent sub-pixel when the sub-pixel is receiving a pixel voltage signal from the data line so that the vertically adjacent sub-pixel unit receives an incorrect pixel voltage signal or a portion thereof. Thus, the generation of such a return current degrades picture quality due to the fact that a voltage of a sub-pixel unit is linked to a voltage of another sub-pixel unit, which is adjacent in the vertical direction.